nicole@portfolio:~/projects/door-monitor$ cat README.md
Automatic Door Monitoring System
Created an automatic door monitoring system using a custom single-cycle RISC-V processor on a Cyclone V FPGA.
FPGA · Verilog · RISC-V
Overview
For my ECE 2300 Digital Logic and Computer Organization final course project, my partner and I developed an automatic door monitoring system using a custom single-cycle RISC-V processor implemented on an Intel Cyclone V FPGA. The processor communicated with a LiDAR sensor through a memory-mapped SPI controller. When an object entered the defined range, an audible piezo buzzer alert would be generated, and a count would be tallied on the FPGA's seven-segment displays.
Design and Implementation
In addition to the processor datapath and control logic, my partner and I developed several memory-mapped peripherals in Verilog, including a seven-segment display driver, 32-bit ALU, SPI controller, and FSM-based multi-note player. In total, this comprised over fifty hardware modules and five thousand lines of both gate-level and register-transfer-level modeling, verified through hundreds of directed and randomized test cases.
On the software side, we wrote eight RISC-V assembly programs totaling over a hundred instructions to interface with the memory-mapped peripherals and test processor functionality. The final application repeatedly requests distance measurements from the LiDAR sensor through the SPI controller and compares each reading against a threshold. When an object enters the monitored range, the FSM-based music player generates an audible alert through the piezo buzzer, while a running person count is updated on the seven-segment displays. Potential future extensions could include a configurable room occupancy limit, multiple operating modes such as day and night, access-restricted alarm controls, and bidirectional people counting using a second distance sensor.